1. Field of the Invention
Embodiments of the present invention generally relate to a processor-based hardware emulation engine and, more particularly, to a selectable write-back processor based emulation system.
2. Description of the Related Art
Hardware emulators are programmable devices used in the verification of hardware designs. A common method of hardware design verification is to use processor-based hardware emulators to emulate the design. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 titled “Clustered Processors In An Emulation Engine”, which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present on an integrated circuit has increased significantly in the past several years. Hardware emulators need to improve in efficiency to keep pace with the increased complexity of integrated circuits. The speed with which a hardware emulator can emulate an integrated circuit is one of the most important benchmarks of the emulator's efficiency, and also one of the emulator's most important selling factors in the emulator market.
A hardware emulator is comprised of multiple processors. The processors are arranged into groups of processors called clusters, and the clusters of procesors collectively comprise the emulation engine. During each process step, each processor is capable of emulating a logic gate, mimicking the function of a logic gate in an integrated circuit. The processors are arranged to compute results in parallel, in the same way logic gates present in an integrated circuit compute many results in parallel. This creates a chain of logic similar to what occurs in an integrated circuit. In the chain of logic, efficient communication between processors is crucial.
The programs executed by the processors in a hardware emulator consist of instructions containing a sequence of operations. Certain operations act directly upon data, while other operations describe the conditions necessary for the data to be acted upon. For example, consider the sequence of operations described by equation 1:if (a!=0)b=c+d  (1)The operation “b=c+d” (b equals c plus d) acts upon the data element “b” using “c” and “d” as operands. The operation “a!=0” (a does not equal zero) describes the condition necessary for data element “b” to be acted upon.
Evaluating conditional operations such as the one described above was previously impossible for a hardware emulator. Therefore, a compiler converts such conditional operations into logically equivalent non-conditional operations. For example, if a, b, c and d are Boolean operands, the above conditional operation may be rewritten as equation 2:b=a&(c+d)|!a&b  (2)There is a drawback to rewriting the sequence of operations shown by equation 1 as the sequence of operations shown by equation 2. Only three memory read ports, i.e., read ports to retrieve the values of a, c and d, are required by a processor to evaluate the first equation. Four memory read ports, i.e., read ports that retrieve the values of a, b, c and d, are required by a processor to evaluate the second equation.
A processor may have to evaluate an instruction that contains a greater number of operands than the processor has read ports. For example, a processor may have four read ports and need to evaluate an instruction word containing six operands. Such an instruction word requires evaluation by at least two processors. The processors may produce several intermediary values during the evaluation of such an instruction word. These intermediary values are of limited use and it would be more beneficial to overwrite the final value stored in memory only when the new final value is different from the value stored in memory.
Thus, there is a need in the art for a processor unit having a selectable write-enable to a memory. The selectable-write enable memory allows the processor unit to write the evaluated output of an instruction word to the memory or maintain the memory in its present state.